1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and a method for etching the same.
2. Description of the Background Art
Recently, the performance and function of semiconductor devices has been advanced. For example, the operating frequency of microprocessors has entered a new “GHz band” era, and a system that mounts a plurality of circuits with different functions on one semiconductor chip, a so-called a system-on-chip (SOC), has entered the field. This semiconductor device employs a multilayer wiring structure in which wirings are formed in a plurality of layers in the thickness direction of the semiconductor device in order to improve its degree of integration. In particular, a multilayer wiring structure referred to as a dual damascene structure has been developed in these years. A dual damascene structure is a further advancement of the damascene structure. In the damascene structure, Cu is used as a wiring material because of its low-resistance and high-electromigration resistance properties, and wiring is implanted with the chemical mechanical polishing (CMP) method. On the other hand, in the dual damascene method, a wiring groove and a via hole are formed in the interlayer insulating film, and a conductive substance such as Cu is simultaneously implanted in the groove and the hole. Thus, an upper layer wiring and a via plug are formed at one time. Therefore, the manufacturing cost of a semiconductor device is reduced in the dual damascene method, compared to a normal damascene method, a so-called single damascene method, in which a wiring groove and a via hole are separately formed.
In a semiconductor device with a multilayer wiring structure, the operation speed of the semiconductor device is highly influenced by not only the resistance value of the wiring itself, but also by the inter-wiring capacitance formed by an interlayer insulating film that is formed in a place between a lower layer wiring and an upper layer wiring. Therefore, the resistance of the wiring itself and the inter-wiring capacitance have to be reduced in order to realize an increase in the operation speed of a semiconductor device. To reduce the inter-wiring capacitance, it is required to reduce the dielectric constant of an interlayer insulating film by using a low dielectric constant film, a so-called a low-k film, as an interlayer insulating film. Also, it is required to take the wiring structure into consideration from the perspective of reducing the effective dielectric constant (keff). In general, the dual damascene structure is classified roughly into two structures. One is the so-called homogeneous structure. This is a unitary structure in which the same type of low-k film is used as the insulating film for a wiring portion and for a via hole portion. The other is the so-called hybrid structure. This is a heterogeneous structure in which different types of low-k films are used as the insulating film for a wiring portion and for a via hole portion. In the homogeneous structure, the depth of the wiring grooves is controlled. Therefore, it is required to use a film with a high dielectric constant, such as a silicon nitride film (relative dielectric constant: k=7.0) and a silicon carbide film (k=4.5) as an etching stopper layer. Because of this, the homogeneous structure has a disadvantage in that the value of the effective dielectric constant (keff) becomes high. On the other hand, in the hybrid structure, it is easy to set the etch selectivity between substances of different low-k film to be higher. Therefore, it is not required to use an etching stopper layer with a high dielectric constant, such as silicon nitride film and silicon carbide film. Because of this, the hybrid structure has an advantage in that the effective dielectric constant (keff) of the whole wiring structure can be reduced, compared to the homogeneous structure.
Japanese Patent Publication JP-A-2002-124568 (especially pages 6-7 and FIG. 2) describes a method for manufacturing a semiconductor device with the hybrid type dual damascene structure. Generally, in manufacturing a dual damascene structure of a semiconductor device, the corners of a hard mask used for forming a wiring groove and a via hole tend to be eliminated and inclined from the perpendicular during the process of etching an interlayer insulating film. This state is called the facet of a hard mask. If a facet state is produced, the wiring size of the hard mask will be wider than the design value. In some cases, this causes a short circuit between a wiring and its adjacent wiring. Because of this, there is a possibility that reliability will be lowered and the yield will be negatively influenced. In a method for manufacturing a semiconductor device described in Japanese Patent Publication JP-A-2002-124568, a facet of a hard mask is prevented in the process of etching by forming at least a layer of a dummy film, which does not exist in the structure at the end of the process of forming a semiconductor device, on the hard mask.
As described above, in manufacturing a dual damascene structure, there is a problem in that a facet of a hard mask is produced in the process of etching an interlayer insulating film. If a facet of a hard mask is produced, acceleration of etching will begin in the portion where the facet is produced, and this will cause a retrograde phenomenon in the hard mask. This phenomenon makes it difficult to form wiring sized at the desired design value. Because of this, there is a possibility that reliability will be lowered and the yield will be negatively influenced.
In the method for manufacturing a semiconductor device described in Japanese Patent Publication JP-A-2002-124568, a protective hard mask is further formed on a hard mask that is required to form a wiring groove and a via hole. Therefore, the number of processes to manufacturing a semiconductor device and the cost thereof are increased in the method.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method for manufacturing a semiconductor device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.